Various polymer coatings are frequently used in semiconductor manufacturing. For example, one such polymer coating is a photoresist or resist layer. Another polymer coating is an antireflection coating (ARC) layer. Still another polymer coating is a planarizing layer of a multiple-resist system. These polymer coatings are typically formed on a wafer substrate by dissolving the polymer in a solvent carrier and applying it to the wafer substrate in liquid form by spin-coating. In spin-coating, the wafer substrate is typically spun at very high speeds between hundreds and thousands of rotations-per-minute (rpm) to achieve a predetermined thickness. The polymer coating is then baked to evaporate out the solvent. Accordingly, the polymer coating is uniformly coated on the wafer substrate if there is an even topography on the substrate. That is, the polymer coating has a flat and/or uniform surface if the surface of the wafer substrate is flat and/or uniform. However, in many situations, the topography of the underlying wafer substrate is not flat and/or uniform. In these situations, spin-coating may result in non-flat and/or non-uniform polymer surface.
One method for flattening and/or planarizing the polymer surface is by chemical-mechanical polish (CMP) which uses a combination of mechanical polishing and chemical reaction. Although CMP is a well-developed technique for flattening and/or planarizing harder material films such as SiO2 and Cu, it has not been adequately developed for flattening and/or planarzing polymer coatings. Even if CMP is successfully developed for polymer coatings in the future, the CMP process is expensive and time consuming. Furthermore, CMP also consumes expensive polishing compounds. Another method for flattening and/or planarizing a polymer layer such as a photoresist layer is by using a double coating of a photoresist and performing a photoresist etch back process to planarize the photoresist layer. However, this method is time consuming and costly due to the additional photoresist coating and extra etch back process.
It is well known that the topography of the wafer substrate will impact the lithography process margin, for example, depth of focus (DOF). Accordingly, various patterned structures such as gate electrodes, metal line, and passive elements on the substrate, when processed in the front end or backend, need to have a material layer, such as a dielectric film, formed thereon, and the material layer may undergo CMP and/or an etch back process to achieve a quasi-planar surface. However, due to pattern density effects and different layout designs, a substantially equivalent planar surface on the wafer cannot be easily achieved with current planarizing techniques, particularly between the isolated areas and pattern dense areas. Furthermore, a polymer material, such as a photoresist, overlying the wafer will also conformably include the uneven surface, and may result in degradation of the lithography process margin.
Therefore, a need exists for a simple and cost-effective method for planarizing a polymer layer overlying a non-uniform surface.